Moore’s Law

Moore’s Law

Gordon Moore: co-founder of Intel

1965 - observed trends in industry - # of transistors on ICs vs. release dates:

Noticed number of transistors doubling with release of each new IC generation

release dates (separate generations) were all 18-24 months apart

Predicted that the number of transistors per chip would grow exponentially (double every 18 months)

Exponential improvement in technology is a natural trend: 

e.g. Steam Engines - Dynamo - Automobile

The level of integration of silicon technology as measured in terms of number of devices per IC

This comes about in two ways – size reduction of the individual devices and increase in the chip or dice size

As an indication of size reduction, it is interesting to note that feature size was measured in mils (1/1000 inch, 1 mil = 25 mm) up to early 1970’s, whereas now all features are measured in mm’s (1 mm = 10-6 m or 10-4 cm)

Semiconductor industry has followed this prediction with surprising accuracy

Amazing visionary – million transistor/chip barrier was crossed in the 1980’s.

2300 transistors, 1 MHz clock (Intel 4004) - 1971

42 Million, 2 GHz clock (Intel P4) - 2001

140 Million transistor (HP PA-8500)

VLSI Applications

VLSI Applications
VLSI is an implementation technology for electronic circuitry - analogue or digital
It is concerned with forming a pattern of interconnected switches and gates on the surface of a crystal of semiconductor
* Microprocessors
* personal computers
* Microcontrollers
* Memory - DRAM / SRAM
* Special Purpose Processors - ASICS (CD players, DSP applications)
* Optical Switches
Has made highly sophisticated control systems mass-producable and therefore cheap

JOBS FOR VLSI ENGINEERS

JOBS FOR VLSI ENGINEERS

As mentioned above, the main job functions in this industry are Design, Product, Test, Applications and Process Engineering. For the sake of clarity, product engineering and test engineering functions are described separately, but it is most efficient to combine these two functions into one engineer because of the interdependency and overlap of skills, tasks and job functions.

1. Design Engineer:

Takes specifications, defines architecture, does circuit design, runs simulations, supervises layout, tapes out the chip to the foundry, evaluates the prototype once the chip comes back from the fab.

2. Product Engineer:

Gets involved in the project during the design phase, ensures manufacturability, develops characterization plan, assembly guidelines, develops quality and reliability plan, evaluates the chip with the design engineer, evaluates the chip through characterization, reliability qualification and manufacturing yield point of view (statistical data analysis). He is responsible for production release and is therefore regarded as a team leader on the project. Post production, he is responsible for customer returns, failure analysis, and corrective actions including design changes.

3. Test Engineer:

Develops test plan for the chip based on specifications and data sheet, creates characterization and production program for the bench test or the ATE (Automatic Test Equipment), designs test board hardware, correlates ATE results with the bench results to validate silicon to compare with simulation results. He works closely with the product engineer to ensure smooth release to production and post release support.

4. Applications Engineer:

Defines new products from system point of view at the customer’s end, based on marketing input. His mission is to ensure the chip works in the system designed or used by the customers, and complies with appropriate standards (such as Ethernet, SONET, WiFi etc.). He is responsible for all customer technical support, firmware development, evaluation boards, data sheets and all product documentation such as application notes, trade shows, magazine articles, evaluation reports, software drives and so on.

5. Process Engineer:

This is a highly specialized function which involves new wafer process development, device modeling, and lots of research and development projects. There are no quick rewards on this job! If you are R&D oriented, highly trained in semiconductor device physics area, do not mind wearing bunny suits (the clean room uniforms used in all fabs), willing to experiment, this job is for you.

6. Packaging Engineer:

This is another highly specialized job function. He develops precision packaging technology, new package designs for the chips, does the characterization of new packages, and does electrical modeling of the new designs.

7. CAD Engineer:

This is an engineering function that supports the design engineering function. He is responsible for acquiring, maintaining or developing all CAD tools used by a design engineer. Most companies buy commercially available CAD tools for schematic capture, simulation, synthesis, test vector generation, layout, parametric extraction, power estimation, and timing closure; but in several cases, these tools need some type of customization. A CAD engineer needs to be highly skilled in the use of these tools, be able to write software routines to automate as many functions as possible and have a clear understanding of the entire design flow

VLSI DESIGNS ARE CLASSIFIED INTO THREE CATEGORIES

VLSI DESIGNS ARE CLASSIFIED INTO THREE CATEGORIES:

1. Analog:

Small transistor count precision circuits such as Amplifiers, Data converters, filters, Phase Locked Loops, Sensors etc.

2. ASICS or Application Specific Integrated Circuits:

Progress in the fabrication of IC's has enabled us to create fast and powerful circuits in smaller and smaller devices. This also means that we can pack a lot more of functionality into the same area. The biggest application of this ability is found in the design of ASIC's. These are IC's that are created for specific purposes - each device is created to do a particular job, and do it well. 

The most common application area for this is DSP - signal filters, image compression, etc. To go to extremes, consider the fact that the digital wristwatch normally consists of a single IC doing all the time-keeping jobs as well as extra features like games, calendar, etc.

3. SoC or Systems on a chip:

These are highly complex mixed signal circuits (digital and analog all on the same chip). A network processor chip or a wireless radio chip is an example of an SoC

VLSI DESIGN PROCESS

THE VLSI DESIGN PROCESS

A typical digital design flow is as follows:

* Specification

* Architecture

* RTL Coding

* RTL Verification

* Synthesis

* Backend

All modern digital designs start with a designer writing a hardware description of the IC (using HDL or Hardware Description Language) in Verilog/VHDL. A Verilog or VHDL program essentially describes the hardware (logic gates, Flip-Flops, counters etc) and the interconnect of the circuit blocks and the functionality. Various CAD tools are available to synthesize a circuit based on the HDL. The most widely used synthesis tools come from two CAD companies. Synposys and Cadence.

Without going into details, we can say that the VHDL, can be called as the "C" of the VLSI industry. VHDL stands for "VHSIC Hardware Definition Language", where VHSIC stands for "Very High Speed Integrated Circuit". This languages is used to design the circuits at a high-level, in two ways. It can either be a behavioural description, which describes what the circuit is supposed to do, or a structural description, which describes what the circuit is made of. There are other languages for describing circuits, such as Verilog, which work in a similar fashion.

Both forms of description are then used to generate a very low-level description that actually spells out how all this is to be fabricated on the silicon chips. This will result in the manufacture of the intended IC.

A typical analog design flow is as follows:

In case of analog design, the flow changes somewhat.

* Specifications

* Architecture

* Circuit Design

* SPICE Simulation

* Layout

* Parametric Extraction / Back Annotation

* Final Design

* Tape Out to foundry

While digital design is highly automated now, very small portion of analog design can be automated. There is a hardware description language called AHDL but is not widely used as it does not accurately give us the behavioral model of the circuit because of the complexity of the effects of parasitic on the analog behavior of the circuit. Many analog chips are what are termed as “flat” or non-hierarchical designs. 

This is true for small transistor count chips such as an operational amplifier, or a filter or a power management chip. For more complex analog chips such as data converters, the design is done at a transistor level, building up to a cell level, then a block level and then integrated at a chip level. 

Not many CAD tools are available for analog design even today and thus analog design remains a difficult art. SPICE remains the most useful simulation tool for analog as well as digital design

VLSI Implementation Media

VLSI Implementation Media

Media requiring fabrication:

* Full Custom - design and physical layout at transistor level
* Standard Cell - design and physical layout at gate/flip-flop level
* Gate Array - design and physical layout at gate level (like standard cell but with some prefabrication of wafer)


Prefabricated media:
* Field Programmable Gate Arrays (FPGAs) - design at gate/flip-flop or register transfer level
* Complex Programmable Logic Devices (CPLDs) - design at gate/flip-flop or register transfer level
* Programmable Logic Devices (PLDs) - design at gate/flip-flop level 
* System-on-Chip (SoC) may incorporate several of these implementation media on a single chip

History of VLSI

VLSI, Very Large Scale Integration

History of VLSI

Late 40s 
Transistor invented at Bell Labs


Late 50s 
First IC (JK-FF by Jack Kilby at TI)


Early 60s 
Small Scale Integration (SSI)     
10s of transistors on a chip


Late 60s 
Medium Scale Integratoin (MSI) 
100s of transistors on a chip


Early 70s 
Large Scale Integration (LSI) 
1000s of transistor on a chip


Early 80s 
VLSI 10,000s of transistors on a chip (later 100,000s & now 1,000,000s)

Ultra LSI is sometimes used for 1,000,000s