VLSI PROJECTS READILY AVAILABLE WITH US
* VLSI Projects only with Simulation @ Low Fees
* VLSI Projects with Hardware Kit & Simulation @ Low Fees - Spartan FPGA 3E KIT
* VLSI Projects with Hardware Kit & Simulation @ Low Fees - CPLD XL, XC Cool Runner
Software Details
Simulation : MODELSIM 6.3G ALTERA
Implementation : XILINX ISE 12.2
Language : VHDL / VERILOG
Power Estimation : Altera XPE or XILINX Power Analyzer
Following Projects are readily available @ NCCT
* A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories
* A Clock Control Strategy for Peak Power and RMSCurrent Reduction Using Path Clustering
* A Computationally Efficient Delay less Frequency-Domain Adaptive Filter Algorithm
* A Linear Programming Based Tone Injection Algorithm for PAPR Reduction of OFDM and Linearly Precoded Systems
* A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks
* A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits
* A Reconfigurable Direct RF Receiver With Jitter Analysis and Applications
* Aliasing-Free Digital Pulse-Width Modulation for Burst-Mode RF Transmitters
* Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
* Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay
* Broadside and Skewed-Load Tests Under Primary Input Constraints
* Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure
* Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip
* Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping
* Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
* Efficiency Optimization for Burst-Mode Multilevel Radio Frequency Transmitters
* Efficient Implementation of Reconfigurable Warped Digital Filters With Variable Low-Pass, High-Pass, Band pass, and Band stop Responses
* Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture
* Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function
* Eliminating Synchronization Latency Using Sequenced Latching
* Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes
* Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits
* Glitch-Free NAND-Based Digitally Controlled Delay-Lines
* IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures
* Low-Power Area-Efficient High-Speed I/O Circuit Techniques
* Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes
* Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic
* Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements
* MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
* Multivoltage Aware Resistive Open Fault Model
* Oscillation and Transition Tests for Synchronous Sequential Circuits
* Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment
* RATS: Restoration-Aware Trace Signal Selection for Post-Silicon Validation
* Reduced-Complexity LCC Reed–Solomon Decoder Based on Unified Syndrome Computation
* Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories
* Smart Reliable Network-on-Chip
* Split-SAR ADCs: Improved Linearity With Power and Speed Optimization
* Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD
* Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches
* The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures
* Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed
* Time-Based All-Digital Technique for Analog Built-in Self-Test
* Two-Tone Phase Delay Control of Center Frequency and Bandwidth in Low-Noise-Amplifier RF Front Ends
* Unique Measurement and Modeling of Total Phase Noise in RF Receiver
* VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture
* WLS Design of Sparse FIR Digital Filters
* VLSI Projects with Hardware Kit & Simulation @ Low Fees - Spartan FPGA 3E KIT
* VLSI Projects with Hardware Kit & Simulation @ Low Fees - CPLD XL, XC Cool Runner
Software Details
Simulation : MODELSIM 6.3G ALTERA
Implementation : XILINX ISE 12.2
Language : VHDL / VERILOG
Power Estimation : Altera XPE or XILINX Power Analyzer
Following Projects are readily available @ NCCT
* A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories
* A Clock Control Strategy for Peak Power and RMSCurrent Reduction Using Path Clustering
* A Computationally Efficient Delay less Frequency-Domain Adaptive Filter Algorithm
* A Linear Programming Based Tone Injection Algorithm for PAPR Reduction of OFDM and Linearly Precoded Systems
* A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks
* A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits
* A Reconfigurable Direct RF Receiver With Jitter Analysis and Applications
* Aliasing-Free Digital Pulse-Width Modulation for Burst-Mode RF Transmitters
* Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
* Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay
* Broadside and Skewed-Load Tests Under Primary Input Constraints
* Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure
* Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip
* Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping
* Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
* Efficiency Optimization for Burst-Mode Multilevel Radio Frequency Transmitters
* Efficient Implementation of Reconfigurable Warped Digital Filters With Variable Low-Pass, High-Pass, Band pass, and Band stop Responses
* Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture
* Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function
* Eliminating Synchronization Latency Using Sequenced Latching
* Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes
* Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits
* Glitch-Free NAND-Based Digitally Controlled Delay-Lines
* IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures
* Low-Power Area-Efficient High-Speed I/O Circuit Techniques
* Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes
* Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic
* Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements
* MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
* Multivoltage Aware Resistive Open Fault Model
* Oscillation and Transition Tests for Synchronous Sequential Circuits
* Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment
* RATS: Restoration-Aware Trace Signal Selection for Post-Silicon Validation
* Reduced-Complexity LCC Reed–Solomon Decoder Based on Unified Syndrome Computation
* Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories
* Smart Reliable Network-on-Chip
* Split-SAR ADCs: Improved Linearity With Power and Speed Optimization
* Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD
* Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches
* The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures
* Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed
* Time-Based All-Digital Technique for Analog Built-in Self-Test
* Two-Tone Phase Delay Control of Center Frequency and Bandwidth in Low-Noise-Amplifier RF Front Ends
* Unique Measurement and Modeling of Total Phase Noise in RF Receiver
* VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture
* WLS Design of Sparse FIR Digital Filters
Call - 044-2823 5816, 98411 93224, 89393 63501
For Abstracts / IEEE Paper, Email us - ncctchennai@gmail.com
For Abstracts / IEEE Paper, Email us - ncctchennai@gmail.com
NCCT
No.109, 2nd Floor, Bombay Flats, Nungambakkam High Road, Nungambakkam, Chennai - 600 034
Near Ganpat Hotel, Above IOB, Next to ICICI Bank, Opp to Cakes'n'Bakes
No.109, 2nd Floor, Bombay Flats, Nungambakkam High Road, Nungambakkam, Chennai - 600 034
Near Ganpat Hotel, Above IOB, Next to ICICI Bank, Opp to Cakes'n'Bakes
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