INTERVIEW QUESTIONS

INTERVIEW QUESTIONS 

Why does the present VLSI circuits use MOSFETs instead of BJTs?

Compared to BJTs, MOSFETs can be made very small as they occupy very small silicon area on IC chip and are relatively simple in terms of manufacturing. Moreover digital and memory ICs can be implemented with circuits that use only MOSFETs i.e. no resistors, diodes, etc.

What are the various regions of operation of MOSFET? How are those regions used?

MOSFET has three regions of operation: the cut-off region, the triode region, and the saturation region.

The cut-off region and the triode region are used to operate as switch. The saturation region is used to operate as amplifier.

What is threshold voltage?

The value of voltage between Gate and Source i.e. VGS at which a sufficient number of mobile electrons accumulate in the channel region to form a conducting channel is called threshold voltage (Vt is positive for NMOS and negative for PMOS).

What does it mean "the channel is pinched off"?

For a MOSFET when VGS is greater than Vt, a channel is induced. As we increase VDS current starts flowing from Drain to Source (triode region). When we further increase VDS, till the voltage between gate and channel at the drain end to become Vt, i.e. VGS - VDS = Vt, the channel depth at Drain end decreases almost to zero, and the channel is said to be pinched off. This is where a MOSFET enters saturation region.

Explain the three regions of operation of a MOSFET

Cut-off region: When VGS < Vt, no channel is induced and the MOSFET will be in cut-off region. No current flows.

Triode region: When VGS ≥ Vt, a channel will be induced and current starts flowing if VDS > 0. MOSFET will be in triode region as long as VDS < VGS - Vt.

Saturation region: When VGS ≥ Vt, and VDS ≥ VGS - Vt, the channel will be in saturation mode, where the current value saturates. There will be little or no effect on MOSFET when VDS is further increased.

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What is channel-length modulation?

In practice, when VDS is further increased beyond saturation point, it does has some effect on the characteristics of the MOSFET. When VDS is increased the channel pinch-off point starts moving away from the Drain and towards the Source. Due to which the effective channel length decreases, and this phenomenon is called as Channel Length Modulation.

Explain depletion region.

When a positive voltage is applied across Gate, it causes the free holes (positive charge) to be repelled from the region of substrate under the Gate (the channel region). When these holes are pushed down the substrate they leave behind a carrier-depletion region.

What is body effect?

Usually, in an integrated circuit there will be several MOSFETs and in order to maintain cut-off condition for all MOSFETs the body substrate is connected to the most negative power supply (in case of PMOS most positive power supply). Which causes a reverse bias voltage between source and body that effects the transistor operation, by widening the depletion region. The widened depletion region will result in the reduction of channel depth. To restore the channel depth to its normal depth the VGS has to be increased. This is effectively seen as change in the threshold voltage - Vt. This effect, which is caused by applying some voltage to body is known as body effect.

Give various factors on which threshold voltage depends.

As discussed in the above question, the Vt depends on the voltage connected to the Body terminal. It also depends on the temperature, the magnitude of Vt decreases by about 2mV for every 1oC rise in temperature.

What is the fundamental difference between a MOSFET and BJT ?

In MOSFET, current flow is either due to electrons(n-channel MOS) or due to holes(p-channel MOS) - In BJT, we see current due to both the carriers.. electrons and holes. BJT is a current controlled device and MOSFET is a voltage controlled device.

Why are most interrupts active low?

If you consider the transistor level of a module, active low means the capacitor in the output terminal gets charged or discharged based on low to high and high to low transition, respectively. when it goes from high to low it depends on the pull down resistor that pulls it down and it is relatively easy for the output capacitance to discharge rather than charging. Hence designers prefer active low interrupt signals.

Which is better: synchronous reset or asynchronous reset signal?

Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for small reset glitches; however, if these glitches occur near the active clock edge, the Flip-flop could go metastable. In some designs, the reset must be generated by a set of internal conditions. A synchronous reset is recommended for these types of designs because it will filter the logic equation glitches between clock.

Problem with synchronous resets is that the synthesis tool cannot easily distinguish the reset signal from any other data signal. Synchronous resets may need a pulse stretcher to guarantee a reset pulse width wide enough to ensure reset is present during an active edge of the clock, if you have a gated clock to save power, the clock may be disabled coincident with the assertion of reset. Only an asynchronous reset will work in this situation, as the reset might be removed prior to the resumption of the clock. Designs that are pushing the limit for data path timing, can not afford to have added gates and additional net delays in the data path due to logic inserted to handle synchronous resets.

Asynchronous reset: The major problem with asynchronous resets is the reset release, also called reset removal. Using an asynchronous reset, the designer is guaranteed not to have the reset added to the data path. Another advantage favoring asynchronous resets is that the circuit can be reset with or without a clock present. Ensure that the release of the reset can occur within one clock period else if the release of the reset occurred on or near a clock edge then flip-flops may go into metastable state.

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Give the expression for CMOS switching power dissipation.

Pswitching = (1/2)CVdd2/f

Where

Pswitching = Switching power.

C = Load capacitance.

Vdd = Supply voltage.

f = Operating frequency.

What is velocity saturation? What are its effects?

In semiconductors, when a strong enough electric field is applied, the carrier velocity in the semiconductor reaches a maximum value. When this happens, the semiconductor is said to be in a state of velocity saturation. As the applied electric field increases from that point, the carrier velocity no longer increases.

In sub-micron technology velocity saturation is an important design characteristic. Velocity saturation greatly affects the voltage transfer characteristics of a circuit. If a semiconductor device enters velocity saturation, an increase in voltage applied to the device will not cause a linear increase in current as would be expected by Ohm's law. Instead, the current may only increase by a small amount, or not at all.

Why are pMOS transistor networks generally used to produce high signals, while nMOS networks are used to product low signals?

This is because threshold voltage effect. A nMOS device cannot drive a full 1 or high and pMOS cant drive full '0' or low. The maximum voltage level in nMOS and minimum voltage level in pMOS are limited by threshold voltage. Both nMOS and pMOS do not give rail to rail swing.

Expand: DTL, RTL, ECL, TTL, CMOS, BiCMOS.

DTL: Diode-Transistor Logic.

RTL: Resistor-Transistor Logic.

ECL: Emitter Coupled Logic.

TTL: Transistor-Transistor Logic.

CMOS: Complementary Metal Oxide Semiconductor.

BiCMOS: Bipolar Complementary Metal Oxide Semiconductor.

On IC schematics, transistors are usually labeled with two, or sometimes one number(s). What do each of those numbers mean?

The two numbers are the width and the length of the channel drawn in the layout. If only one number is present then it is the width of the channel, combined with a default length of the channel.

On what factors does the resistance of metal depend on?

R = (p.l)/A

Where

R = Resistance of the metal.

p = Resistivity of the metal.

A = is the cross sectional area.

l = length of the metal.

With increase in length or decrease in cross sectional area resistance of the metal wire increases. Resistivity(p) is the material property which depends on temperature. In general, resistivity of metals increases with temperature.

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Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four?

To limit the height of the stack. The higher the stack the slower the gate will be. In NAND and NOR gates the number of gates present in the stack is usually same as the number of inputs plus one. So inputs are limited to four.

What are the important aspects of VLSI optimization?

Power, Area, and Speed.

What are the sources of power dissipation?

Dynamic power consumption, due to logic transitions causing logic gates to charge/discharge load capacitance.

Short-circuit current, this occurs when p-tree and n-tree shorted (for a while) during logic transition.

Leakage current, this is a very important source of power dissipation in nano technology, it increases with decrease in lambda value. It is caused due to diode leakages around transistors and n-wells.

What is the need for power reduction?

Low power increases noise immunity, increases batter life, decreases cooling and packaging costs.

Give some low power design techniques.

Voltage scaling, transistor resizing, pipelining and parallelism, power management modes like standby modes, etc.

Give a disadvantage of voltage scaling technique for power reduction.

When voltage is scaled, designers tend to decrease threshold voltage to maintain good noise margins. But decreasing threshold voltages increases leakage currents exponentially.

Give an expression for switching power dissipation.

Pswitching = (1/2)CVdd2/f

Where

Pswitching = Switching power.

C = Load capacitance.

Vdd = Supply voltage.

f = Operating frequency.

Will glitches in a logic circuit cause power wastage?

Yes, because they cause unexpected transitions in logic gates.

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What is the major source of power wastage in SRAM?

To read/write a word data, activates a word line for a row which causes all the columns in the row to be active even though we need only a word data. This consumes a lot power.

What is the major problem associated with caches w.r.t low power design? Give techniques to overcome it.

Cache is a very important part of the integrated chips, they occupy most of the space and hence contain lot of transistors. More transistors means more leakage current. That is the major problem associated with caches w.r.t. low power design. The following techniques are used to overcome it: Vdd-Gating, Cache decay, Drowsy caches, etc.

Does software play any role in low power design?

Yes, one can redesign a software to reduce power consumptions. For example modify the process algorithm which uses less number of computations. 

Why is NAND gate preferred over NOR gate for fabrication?

NAND is a better gate for design than NOR because at the transistor level the mobility of electrons of NAND is normally three times that of holes compared to NOR and thus the NAND is a faster gate. The gate-leakage in NAND structures is much lower. If you consider t_phl and t_plh delays you will find that it is more symmetric in case of NAND (the delay profile), but for NOR, one delay is much higher than the other(obviously t_plh is higher since the higher resistance PMOSs are in series connection which again increases the resistance).

Which transistor has higher gain: BJT or MOSFET and why?

BJT has higher gain because it has higher transconductance.This is because the current in BJT is exponentially dependent on input where as in MOSFET it is square law.

Why PMOS and NMOS are sized equally in a transmission gates?

In transmission gate, PMOS and NMOS aid each other rather than competing with each other. So they are sized similarly.

What is SCR?

A silicon-controlled rectifier (or semiconductor-controlled rectifier) is a 4-layer solid state device that controls current flow.

An SCR is a type of rectifier, controlled by a logic gate signal. It is a 4-layered, 3-terminal device. A p-type layer acts as an anode and an n-type layer as a cathode; the p-type layer closer to the n-type(cathode) acts as a gate.

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In CMOS digital design, why is the size of PMOS is generally higher than that of the NMOS?

In PMOS the carriers are holes whose mobility is less than the electrons, the carriers in NMOS. That means PMOS is slower than NMOS. In CMOS technology, NMOS helps in pulling down the output to ground and PMOS helps in pulling up the output to Vdd. If the sizes of PMOS and NMOS are the same, then PMOS takes long time to charge up the output node. If we have a larger PMOS than there will be more carriers to charge the node quickly and overcome the slow nature of PMOS. All this is done to get equal rise and fall times for the output node.

What is slack?

The slack is the time delay difference from the expected delay to the actual delay in a particular path. Slack can be positive or negative.

What is latch up?

A latchup is the inadvertent creation of a low-impedance path between the power supply rails of an electronic component, triggering a parasitic structure(The parasitic structure is usually equivalent to a thyristor or SCR), which then acts as a short circuit, disrupting proper functioning of the part. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical over stress - EOS.

Why is the size of inverters in buffer design gradually increased? Why not give the output of a circuit to one large inverter?

Because circuit can not drive the high output load straight away, so the load is gradually increased, by gradually increasing the size of inverters to get an optimized performance.

What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus?

The charge sharing problem occurs when the charge which is stored at the output node in the phase is shared among the output or junction capacitances of transistors which are in the evaluation phase. Charge sharing may degrade the output voltage level or even cause erroneous output value.

In the serially connected NMOS logic the input capacitance of each gate shares the charge with the load capacitance by which the logical levels drastically mismatched than that of the desired once. To eliminate this load capacitance must be very high compared to the input capacitance of the gate, which is generally 10 times.

What happens to delay if load capacitance is increased?

Delay increases.

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